1. Field of the Invention
The present invention relates to an apparatus for random parity check and correction with BCH code and, more particularly, to an apparatus applicable to flash data writing and capable of BCH encoding and decoding, and random parity checking and correction with BCH code.
2. The Related Arts
Flash memory is widely used in many digital equipments, such as, flash drives, and MP3 players. However, during the writing to the flash memory, it is necessary to perform the parity checking and correction on the codes written to the flash memory to ensure the correctness of the data.
The conventional parity check and correction of the flash memory data access uses the byte-based Reed-Solomon code. The encoder and the decoder of the Reed-Solomon code is more complicated. For example, the encoder includes a parity check unit b(x), generator polynomial g(x), encoding vector v(x), and message u(x), and the relations among them are:
            g      ⁡              (        x        )              =          1      +                        g          1                ⁢        x            +                        g          2                ⁢                  x          2                    +                        g          3                ⁢                  x          3                    +              …        ⁢                                  ⁢                  g                      n            -            k            -            1                          ⁢                  x                      n            -            k            -            1                              +              x                  n          -          k                                v      ⁡              (        x        )              =                  u        ⁡                  (          x          )                    *              g        ⁡                  (          x          )                                                              v            ⁡                          (              x              )                                =                    ⁢                                    b              ⁡                              (                x                )                                      +                                          x                                  n                  -                  k                                            ⁢                              u                ⁡                                  (                  x                  )                                                                                                  =                    ⁢                                    b              0                        +                                          b                1                            ⁢              x                        +                          …              ⁢                                                          ⁢                              b                                  n                  -                  k                  -                  1                                            ⁢                              x                                  n                  -                  k                  -                  1                                                      +                                          u                0                            ⁢                              x                                  n                  -                  k                                                      +                                          u                1                            ⁢                              x                                  n                  -                  k                  -                  1                                                      +            …            +                                                                  ⁢                                    u                              k                ⁢                                                                  ⁢                1                                      ⁢                          x                              n                -                1                                                                                  =                    ⁢                      [                                          b                0                            ,                              b                1                            ,                              …                ⁢                                                                  ⁢                                  b                                      n                    -                    k                    -                    1                                                              ,                              u                0                            ,                              u                1                            ,                              …                ⁢                                                                  ⁢                                  u                                      k                    -                    1                                                                        ]                              
The above polynomial relation ids disclosed as in FIG. 1 of a conventional parity check encoder circuit. The parity check computation units b0-bn-k-1 are added, and the generator polynomial units g0-gn-k-1 are multiplied. The conventional parity check encoder circuit requires 4096 cycles to shift to the last stage of parity check unit bn-k-1. The problem of long computation time is a major drawback of error parity checking and correction.
In addition, the conventional parity check encoder circuit uses Reed-Solomon code for computing the eigen value, error address polynomial, and error address, which requires a longer computing time. Also, the conventional parity check encoder circuit requires at least fourteen 13-bit multipliers and twelve 13-bit adders to accomplish the computation. The circuit is more complex and the manufacturing cost is high.
Taiwan Patent No. 1226758 disclosed an apparatus and method for encoding interleaved periodic code, which is a typical Reed-Solomon code parity check and correction. That is, the disclosed patent also has the drawbacks of long computing time and high hardware cost.